The present disclosure relates generally to integrated circuits (ICs), and more particularly to a system and method for providing data retention with reduced power consumption.
Many portable electronic devices such as cellular phones, digital cameras/camcorders, personal digital assistants, laptop computers and video games operate on batteries. During periods of inactivity the device may not perform processing operations and may be placed in a power-down or standby power mode to conserve power. Power provided to ICs within the electronic device may be turned off in a standby power mode. However, presence of leakage current during the standby power mode represents a challenge for designing portable, battery operated devices. Data retention circuits such as flip-flops and/or latches within the device may be used to store status information for later use prior to the device entering the standby power mode. The data retention latch, which may also be referred to as a shadow latch or a balloon latch, is typically powered by a separate ‘always on’ power supply.
A known technique for reducing leakage current during periods of inactivity utilizes multi-threshold CMOS (MTCMOS) technology to implement the shadow latch. In this approach, the shadow latch utilizes thick gate oxide transistors and/or high threshold voltage (Vt) transistors to reduce the leakage current in standby power mode. The shadow latch is typically detached from the rest of the circuit during normal operation (e.g., during an active power mode) to maintain performance. To retain data in a ‘master-slave’ flip-flop topology, a third latch, e.g., the shadow latch, is added to the master latch and the slave latch for the data retention.
Some of the MTCMOS technology based data retention techniques such as the shadow latch are described in further detail in the following technical papers and U.S. patent applications, which are hereby incorporated herein by reference into this specification: 1) “Low Powered Integrated Scan-Retention Mechansim”, V. Zyuban, et al., ISPLED 2002, Aug. 12-14, 2002, Monterey, Calif. (Copyrighted Paper), 2) “A 1-V High-Speed MTCMOS Circuit Scheme for Power-Down Application Circuits”, Shigematsu, et al., IEEE Journal of Solid-State Circuits, Volume 32, No. 6, June 1997, 3) US Patent Application No. 20040051574, Ko Uming, et al., entitled ‘Retention Register With Normal Functionality Independent Of Retention Power Supply’, and 4) US Patent Application No. 20040008071, Ko Uming, et al., entitled ‘Retention Register For System-Transparent State Retention’.
However, known techniques for data retention such as use of the shadow latch may result in an increased area and increased cost per flip-flop. The additional area needed for the shadow latch per flip flop is magnified at the chip level when a very large number of data retention flip-flops may be used. In addition, the shadow latch may not be able to operate at lower operating voltages. Due to the higher threshold voltage (Vt) of the shadow latch transistors, transferring flip-flop data in and out of the shadow latch may get slower as the supply voltage is lowered.
Therefore, a need exists to provide an improved method and system for providing data retention with reduced power consumption in a standby power mode. Additionally, a need exists to reduce the area overhead associated with the data retention flip-flop. Furthermore, a need exists to operate the data retention flip-flop with a scalable supply voltage. Accordingly, it would be desirable to provide an improved data retention flip-flop, absent the disadvantages found in the prior techniques discussed above.